1. Field of the Invention
The present invention relates to a method of generating a data pattern similar to an 8B/10B code and an apparatus for generating such a data pattern, more particularly to a method of generating such a data pattern as a test pattern for verifying the performance of a serializer and an apparatus for generating such a data pattern.
2. Description of the Related Art
Recently, high-speed I/O (Input/Output) interface devices are usually used in order to overcome the limit of parallel data bus.
FIG. 1 is a schematic view of the Related Art showing a general n:1 serializer 100, which is an example of a high-speed I/O interface device, and FIG. 2 is a schematic view of the Related Art showing a waveform of serialized data output from n:1 serializer 100 of FIG. 1.
Referring to FIGS. 1 and 2, data D<1>, D<2>, . . . , D<n−1> are provided in parallel to, and serialized by, serializer 100. Thus, serialized data D<1>, D<2>, . . . D<n−1> are sequentially output from serializer 100. The performance of serializer 100 can be tested by providing its parallel input terminals with a PRBS test pattern (in parallel).
A known pseudo random bit sequence (PRBS) generator stores a data pattern in memory, e.g., in a ROM (Read Only Memory) table, and generates the data pattern by reading from the memory. The known PRBS generator using the ROM table is well suited to a test device for which physical size and power consumption are not significant design constraints. However, the known PRBS generator using the ROM table is not well suited to being implemented in a semiconductor chip which typically should consume a small area and a small amount of power.
FIG. 3 is a schematic view of the Related Art showing such a general PRBS generator 300, and FIG. 4 is a timing diagram showing an output X1 of PRBS generator 300 of FIG. 3. PRBS generator 300 of FIG. 3 implements the polynomial of f(x)=X7+X6+1.
Referring to FIG. 3, PRBS generator 300 is formed of cascade-connected shift registers SR1–SR7. Signals X1 and X2, which are the outputs of shift registers SR1 and SR2, are input to an XOR gate 301. A signal X8, which is the output of XOR gate 301, can be described as X8(n)=X1(n)⊕X2(n). Shift registers SR1 through SR7 respectively have a non-zero initial value. A PRBS is outputted in synchronization with a clock signal CLK from PRBS generator 300. For example, as shown in FIG. 4 (according to the Related Art), PRBS generator 300 outputs signal X1 having a random binary value in synchronization with clock signal CLK.
An example of a known 8 bit PRBS generator, which is used as a parallel scrambler of an ATM (Asynchronous Transfer Mode) exchange, is disclosed in U.S. Patent Application laid-open publication-No. 2002/0051542 (entitled “PARALLEL SCRAMBLER OF EXCHANGE IN ASYNCHRONOUS TRANSFER MODE”).
In a wire-connected (hereafter, wired) communication network, data are typically encoded into an 8B/10B code (in which 8 bit bytes are encoded into 10 bit bytes) and the 8B/10B code is transmitted/received via wire-connections through the communication network. The Related Art PRBS that is used as a test pattern for the Related Art serializer significantly differs from the 8B/10B code. For example, such a Related Art PRBS test pattern can have seven consecutive “1” ( . . . 1111111 . . . ), or six consecutive “0”s ( . . . 000000 . . . ).